参考文献 References
[1] K. Lee, S. Kim, J.-H. Lee, D. Kwon, and B.-G. Park, "Analysis on Reverse Drain-Induced Barrier Lowering and Negative Differential Resistance of Ferroelectric-Gate Field-Effect Transistor Memory,"Ieee Electr Device L, vol. 41, no. 8, pp. 1197-1200, 2020.
[2] C. Jin, T. Saraya, T. Hiramoto, and M. Kobayashi, "Physical Mechanisms of Reverse DIBL and NDR in FeFETs with Steep Subthreshold Swing,"Ieee J Electron Devi, vol. 8, pp. 429-434, 2020.
[3] C. Jin, T. Saraya, T. Hiramoto, and M. Kobayashi, "Physical Mechanisms of Reverse DIBL and NDR in FeFETs with Steep Subthreshold Swing,"Ieee J Electron Devi, vol. 8, pp. 429-434, 2020.
[4] H. Amrouch et al., "Impact of Variability on Processor Performance in Negative Capacitance FinFET Technology," (in English), Ieee T Circuits-I, vol. 67, no. 9, pp. 3127-3137, Sept 2020. Electron Dev, vol. 68, no. 3, pp. 1202-1206, 2021.
[5] A. Sharma and K. Roy, "1T Non-Volatile Memory Design Using Sub-10nm Ferroelectric FETs,"Ieee Electr Device L, vol. 39, no. 3, pp. 359-362, 2018
[6] J. R. Zhou et al., "Incomplete Dipoles Flipping Produced Near Hysteresis-Free Negative Capacitance Transistors," (in English), Ieee Electr Device L, vol. 40, no. 2, pp. 329-332, Feb 2019..
[7] 肖长江,窦志强, "钙钛矿铁电体在超高压下的相变研究进展,"人工晶体学报, vol. 47, no. 01, pp. 194-199, 2018.
[8] L. Qiao et al., "Observation of negative capacitance in antiferroelectric PbZrO3 Films,"Nat Commun, vol. 12, no. 1, p. 4215, Jul 9 2021.
[9] 陈大凯, 蔡苇, 周创,吴红迪,符春林, "Ca_3Ti_2O_7杂化非本征铁电体的制备及其掺杂改性研究进展,"电子元件与材料, vol. 40, no. 10, pp. 983-989+1027, 2021.
[10] W. W. Gao et al., "Room-Temperature Negative Capacitance in a Ferroelectric Dielectric Super lattice Heterostructure," (in English), Nano Lett, vol. 14, no. 10, pp. 5814-5819, Oct 2014
[11] Y. K. Lin et al., "Spacer Engineering in Negative Capacitance FinFETs," (in English), Ieee Electr Device L, vol. 40, no. 6, pp. 1009-1012, Jun 2019.
[12] V. Chauhan, D. P. Samajdar, N. Bagga, and A. Dixit, "A Novel Negative Capacitance FinFET with Ferroelectric Spacer: Proposal and Investigation,"IEEE Trans Ultrason Ferroelectr Freq Control, vol. PP, Jul 19 2021.
[13] O. Prakash, N. Chauhan, A. Gupta, and H. Amrouch, "Performance Optimization of Analog Circuits in Negative Capacitance Transistor Technology,"Microelectron J, vol. 115, 2021.
[14] K. Lee, J.-H. Bae, S. Kim, J.-H. Lee, B.-G. Park, and D. Kwon, "Ferroelectric-Gate Field-Effect Transistor Memory With Recessed Channel,"Ieee Electr Device L, vol. 41, no. 8, pp. 1201-1204, 2020
[15] S. Wang et al., "Design of negative capacitance tunneling field effect transistor with dual-source U-shape channel, super-steep subthreshold swing and large on-state current,"Superlattice Microst, vol. 155, 2021.
[16] X. Wang et al., "Impact of Charges at Ferroelectric/ Interlayer Interface on Depolarization Field of Ferroelectric FET With Metal/Ferroelectric/ Interlayer/Si Gate-Stack," Ieee T Electron Dev, vol. 67, no. 10, pp. 4500-4506, 2020..
[17] T. Yu, W. Lü, Z. Zhao, P. Si, and K. Zhang, "Effect of different capacitance matching on negative capacitance FDSOI transistors,"Microelectron J, vol. 98, 2020.
[18] M.-Y. Kao et al., "Optimization of NCFET by Matching Dielectric and Ferroelectric Nonuniformly Along the Channel,"Ieee Electr Device L, vol. 40, no. 5, pp. 822-825, 2019.
[19] 李珍, "负电容场效应晶体管器件模型及仿真研究," 硕士, 电子科技大学, 2020.
[20] 李珍,翟亚红, "铁电负电容场效应晶体管器件的研究,"压电与声光, vol. 41, no. 06, pp. 782-785, 2019.
[21] W.-X. You, P. Su, and C. Hu, "Evaluation of NC-FinFET Based Subsystem-Level Logic Circuits,"Ieee T Electron Dev, vol. 66, no. 4, pp. 2004-2009, 2019.
[22] "Electron Devices; Reports on Electron Devices Findings from University of California Provide New Insights (Proposal for Capacitance Matching In Negative Capacitance Field-effect Transistors),"Electronics Newsweekly, 2019.
[23] 潘奥霖, 杜爱民, "氧化铪基铁电场效应晶体管存储器研究进展,"半导体技术, vol. 46, no. 10, pp. 745-753+800, 2021.
[24] P. Wang et al., "Drain–Erase Scheme in Ferroelectric Field-Effect Transistor—Part I: Device Characterization," Ieee T Electron Dev, vol. 67, no. 3, pp. 955-961, 2020.
[25] W.-D. Liu, Z.-Y. Huang, J. Ma, Z.-W. Zheng, and C.-H. Cheng, "Impact of Series-Connected Ferroelectric Capacitor in HfO₂-Based Ferroelectric Field-Effect Transistors for Memory Application,"Ieee J Electron Devi, vol. 8, pp. 1076-1081, 2020.
[26] P. Lu et al., "Source/Drain Extension Doping Engineering for Variability Suppression and Performance Enhancement in 3-nm Node FinFETs,"Ieee T Electron Dev, vol. 68, no. 3, pp. 1352-1357, 2021.
[27] H. Mulaosmanovic et al., "Investigation of Accumulative Switching in Ferroelectric FETs: Enabling Universal Modeling of the Switching Behavior,"Ieee T Electron Dev, vol. 67, no. 12, pp. 5804-5809, 2020.
[28] W. Shim and S. Yu, "Technological Design of 3D NAND-Based Compute-in-Memory Architecture for GB-Scale Deep Neural Network,"Ieee Electr Device L, vol. 42, no. 2, pp. 160-163, 2021.
[29] W. Deng, H. Yang, and D. Wu, "Low-Frequency Noise Analysis of the Optimized Post High-k Deposition Annealing in FinFET Technology,"Ieee T Electron Dev, vol. 68, no. 3, pp. 1202-1206, 2021.
[30] A. I. Khan et al., "Negative Capacitance in Short-Channel FinFETs Externally Connected to an Epitaxial Ferroelectric Capacitor," (in English), Ieee Electr Device L, vol. 37, no. 1, pp. 111-114, Jan 2016
[31] 周家伟 徐礼磊 葛凡等, "负电容场效应晶体管研究进展,"ELECTRONICS WORLD・探索与观察, vol. 23, no. 12, pp.27-28, 2020.
[32] C. Liu et al., "Simulation-based study of negative- capacitance double-gate tunnel field-effect transistor with ferroelectric gate stack,"Jpn J Appl Phys, vol. 55, no. 4S, 2016.
[33] A. J. Tan et al., "Experimental Demonstration of a Ferroelectric HfO2-Based Content Addressable Memory Cell,"Ieee Electr Device L, vol. 41, no. 2, pp. 240-243, 2020.
[34] K. Jang, T. Saraya, M. Kobayashi, and T. Hiramoto, "I-on/I-off ratio enhancement and scalability of gate-all- around nanowire negative-capacitance FET with ferroelectric HfO2," (in English), Solid State Electron, vol. 136, pp. 60-67, Oct 2017.
[35] H. Mulaosmanovic et al., "Investigation of Accumulative Switching in Ferroelectric FETs: Enabling Universal Modeling of the Switching Behavior,"Ieee T Electron Dev, vol. 67, no. 12, pp. 5804-5809, 2020.
[36] P. Wang et al., "Investigating Ferroelectric Minor Loop Dynamics and History Effect—Part II: Physical Modeling and Impact on Neural Network Training,"Ieee T Electron Dev, vol. 67, no. 9, pp. 3598-3604, 2020.
[37] 吴迪, 徐永珍, 姜毅,刘会刚, "低亚阈值摆幅铝掺杂二氧化铪铁电材料金属-铁电层-绝缘层-半导体场效晶体管研究(英文),"南开大学学报(自然科学版), vol. 54, no. 02, pp. 52-57, 2021.
[38] H. Mulaosmanovic et al., "Impact of Read Operation on the Performance of HfO2-Based Ferroelectric FETs," Ieee Electr Device L, vol. 41, no. 9, pp. 1420-1423, 2020.
[39] M. Kobayashi and T. Hiramoto, "On device design for steep-slope negative-capacitance field-effect-transistor operating at sub-0.2V supply voltage with ferroelectric HfO2 thin film,"Aip Adv, vol. 6, no. 2, 2016.
[40] J. Y. Kim, M.-J. Choi, and H. W. Jang, "Ferroelectric field effect transistors: Progress and perspective,"Apl Mater, vol. 9, no. 2, 2021.
[41] 李俊, 杨阳, 吴振华, 杨文, 李成,陈松岩, "基于低势垒FM/I/n-Si磁隧道结的优化自旋注入效率和增强的Spin MOSFET信号,"第十二届全国硅基光电子材料及器件研讨会, 中国福建厦门, 2017, p. 2.
[42] "Dirac-source field-effect transistors as energy- efficient,high-performance electronic switches," Science Foundation in China, vol. 26, no. 03, p. 46, 2018.
[43] J.-H. Bae et al., "Highly Scaled, High Endurance, Ω-Gate, Nanowire Ferroelectric FET Memory Transistors,"Ieee Electr Device L, vol. 41, no. 11, pp. 1637-1640, 2020.
[44] T. Yu, W. Lü, Z. Zhao, P. Si, and K. Zhang, "Negative drain-induced barrier lowering and negative differential resistance effects in negative-capacitance transistors," Microelectron J, vol. 108, 2021.
[45] 肖永光, "铁电场效应晶体管的保持性能与负电容效应研究," 博士, 湘潭大学, 2013.
[46] Y. H. Liang, Z. M. Zhu, X. Q. Li, S. K. Gupta, S. Datta, and V. Narayanan, "Mismatch of Ferroelectric Film on Negative Capacitance FETs Performance," (in English), Ieee T Electron Dev, vol. 67, no. 3, pp. 1297-1304, Mar 2020.
[47] Y. Liu et al., "Investigation of the Impact of Externally Applied Out-of-Plane Stress on Ferroelectric FET,"Ieee Electr Device L, vol. 42, no. 2, pp. 264-267, 2021.
[48] E. Ko, H. Lee, Y. Goh, S. Jeon, and C. Shin, "Sub-60-mV / decade Negative Capacitance FinFET With Sub-10-nm Hafnium-Based Ferroelectric Capacitor," (in English), Ieee J Electron Devi, vol. 5, no. 5, pp. 306-309, Sep 2017.
[49] A. D. Gaidhane, A. Verma, and Y. S. Chauhan, "Study of multi-domain switching dynamics in negative capacitance FET using SPICE model,"Microelectron J, vol. 115, 2021.
[50] E. Ko, J. W. Lee, and C. Shin, "Negative Capacitance FinFET With Sub-20-mV/decade Subthreshold Slope and Minimal Hysteresis of 0.48 V," (in English), Ieee Electr Device L, vol. 38, no. 4, pp. 418-421, Apr 2017.
[51] R. Rasool, D. Najeeb ud, and G. M. Rather, "RETRACTED ARTICLE: An analytical model for the effects of the variation of ferroelectric material parameters on the minimum subthreshold swing of NC-FETs,"J Comput Electron, vol. 18, no. 4, pp. 1207-1213, 2021.
[52] S. Semwal and A. Kranti, "Insights into unconventional behaviour of negative capacitance transistor through a physics-based analytical model,"Semicond Sci Tech, vol. 36, no. 9, 2021.
[53] H. Mulaosmanovic et al., "Interplay Between Switching and Retention in HfO2-Based Ferroelectric FETs,"Ieee T Electron Dev, vol. 67, no. 8, pp. 3466-3471, 2020.
[54] M. Lederer et al., "Integration of Hafnium Oxide on Epitaxial SiGe for p-type Ferroelectric FET Application,"Ieee Electr Device L, vol. 41, no. 12, pp. 1762-1765, 2020.
[55] C.-J. Sun et al., "Comprehensive Study of Inversion and Junctionless Ge Nanowire Ferroelectric HfZrO Gate-All-Around FETs Featuring Steep Subthreshold Slope with Transient Negative Capacitance,"ECS Journal of Solid State Science and Technology, vol. 10, no. 6, 2021.
[56] F. I. Sakib, F. E. Mullick, S. Shahnewaz, S. Islam, and M. Hossain, "Influence of device architecture on the performance of negative capacitance MFMIS transistors,"Semicond Sci Tech, vol. 35, no. 2, 2020.
[57] D. Kwon et al., "Negative Capacitance FET With 1.8-nm-Thick Zr-Doped HfO2 Oxide," (in English), Ieee Electr Device L, vol. 40, no. 6, pp. 993-996, Jun 2019.
[58] T. Ali et al., "A Study on the Temperature-Dependent Operation of Fluorite-Structure-Based Ferroelectric HfO2 Memory FeFET: Pyroelectricity and Reliability,"Ieee T Electron Dev, vol. 67, no. 7, pp. 2981-2987, 2020.
[59] 王步冉, 李珍, 谭欣,翟亚红, "铁电负电容可测试性的仿真研究,"微电子学, vol. 49, no. 05, pp. 724-728, 2019.
[60] L. Liu, X. Hou, H. Zhang, J. Wang, and P. Zhou, "Ferroelectric field-effect transistors for logic and in-situ memory applications,"Nanotechnology, vol. 31, no. 42, p. 424007, Jun 29 2020
[61] 吴春香,仲崇贵, "二维铁电材料的第一性原理研究进展,"电子科技, vol. 34, no. 10, pp. 81-86, 2021.
[62] 殷泽润, "有机铁电聚合物薄膜制备及性能特性研究," 硕士, 华东师范大学, 2020e Electr Device L, vol. 28, no. 8, pp. 743-745, 2007.
[63] F. I. Sakib, M. A. Hasan, and M. Hossain, "Exploration of Negative Capacitance in Gate-All-Around Si Nanosheet Transistors," (in English), Ieee T Electron Dev, vol. 67, no. 11, pp. 5236-5242, Nov 2020
[64] K. Karda, A. Jain, C. Mouli, and M. A. Alam, "An anti-ferroelectric gated Landau transistor to achieve sub-60 mV/dec switching at low voltage and high speed,"Appl Phys Lett, vol. 106, no. 16, 2015.
[65] 周久人, "基于铁电材料的负电容场效应晶体管研究," 博士, 西安电子科技大学, 2019.
[66] A. Lu, X. Peng, Y. Luo, and S. Yu, "Benchmark of the Compute-in-Memory-Based DNN Accelerator With Area Constraint,"Ieee T Vlsi Syst, vol. 28, no. 9, pp. 1945-1952, 2020.
[67] K. Tamersit, "A computational study of short-channel effects in double-gate junctionless graphene nanoribbon field-effect transistors,"J Comput Electron, vol. 18, no. 4, 2019.
[68] S.-Y. Lee, C.-C. Lee, Y.-S. Kuo, S.-W. Li, and T.-S. Chao, "Ultrathin Sub-5-nm Hf₁₋ₓZrₓO₂ for a Stacked Gate-all-Around Nanowire Ferroelectric FET With Internal Metal Gate,"Ieee J Electron Devi, vol. 9, pp. 236-241, 2021.
[69] 赵雯等, "22nm FDSOI工艺SRAM单粒子效应的重离子实验研究,"原子能科学技术, pp. 1-9.
[70] "Electron Devices; Reports on Electron Devices Findings from University of California Provide New Insights (Proposal for Capacitance Matching In Negative Capacitance Field-effect Transistors),"Electronics Newsweekly, 2019.
[71] W.-X. You, P. Su, and C. Hu, "A New 8T Hybrid Nonvolatile SRAM With Ferroelectric FET,"Ieee J Electron Devi, vol. 8, pp. 171-175, 2020.
[72] 林翠, 白刚, 李卫,高存法, "外延PbZr_(0.2)Ti_(0.8)O_3薄膜负电容的应变调控,"物理学报, vol. 70, no. 18, pp. 318-326, 2021.
[73] V. Chauhan and D. P. Samajdar, "Recent Advances in Negative Capacitance FinFETs for Low-Power Applications: A Review,"IEEE Trans Ultrason Ferroelectr Freq Control, vol. 68, no. 10, pp. 3056-3068, Oct 2021.
[74] D. Madadi and A. A. Orouji, "Investigation of 4H-SiC gate-all-around cylindrical nanowire junctionless MOSFET including negative capacitance and quantum confinements,"The European Physical Journal Plus, vol. 136, no. 7, 2021.ron Dev, vol. 66, no. 6, pp. 2538-2543, Jun 2019.
[75] K. Tamersit, M. K. Q. Jooq, and M. H. Moaiyeri, "Analog/RF performance assessment of ferroelectric junctionless carbon nanotube FETs: A quantum simulation study,"Physica E: Low-dimensional Systems and Nanostructures, vol. 134, 2021.
[76] S. E. Huang, C. L. Yu, and P. Su, "Investigation of Fin-Width Sensitivity of Threshold Voltage for InGaAs and Si Negative-Capacitance FinFETs Considering Quantum-Confinement Effect," (in English), Ieee T Electron Dev, vol. 66, no. 6, pp. 2538-2543, Jun 2019.
[77] H. Agarwal et al., "Proposal for Capacitance Matching in Negative Capacitance Field-Effect Transistors," (in English), Ieee Electr Device L, vol. 40, no. 3, pp. 463-466, Mar 2019.
[78] W. Huang et al., "Investigation of negative DIBL effect for ferroelectric-based FETs to improve MOSFETs and CMOS circuits,"Microelectron J, vol. 114, 2021.
[79] N. Zagni, P. Pavan, and M. A. Alam, "Two-dimensional MoS2 negative capacitor transistors for enhanced (super-Nernstian) signal-to-noise performance of next-generation nano biosensors,"Appl Phys Lett, vol. 114, no. 23, 2019.
[80] X. Chen et al., "The Impact of Ferroelectric FETs on Digital and Analog Circuits and Architectures,"IEEE Design & Test, vol. 37, no. 1, pp. 79-99, 2020.
[81] R. Rajaei, M. M. Sharifi, A. Kazemi, M. Niemier, and X. S. Hu, "Compact Single-Phase-Search Multistate Content-Addressable Memory Design Using One FeFET/Cell,"Ieee T Electron Dev, vol. 68, no. 1, pp. 109-117, 2021.
[82] J. Huo et al., "Investigation on negative capacitance FinEFT beyond 7 nm node from device to circuit," Microelectron J, vol. 116, 2021.
[83] H. Eslahi, T. J. Hamilton, and S. Khandelwal, "Small signal model and analog performance analysis of negative capacitance FETs,"Solid State Electron, vol. 186, 2021.
[84] Y. Xiang et al., "Compact Modeling of Multidomain Ferroelectric FETs: Charge Trapping, Channel Percolation, and Nucleation-Growth Domain Dynamics,"Ieee T Electron Dev, vol. 68, no. 4, pp. 2107-2115, 2021.
[85] "<1.3 Future Scaling_ Where Systems and Technology Meet.pdf>."
[86] J.-D. Chen et al., "Recent research progress of ferroelectric negative capacitance field effect transistors,"Acta Phys Sin-Ch Ed, vol. 69, no. 13, 2020.
[87] 田志,谢欣云, "应力技术改善CMOS器件性能研究进展,"中国集成电路, vol. 21, no. 05, pp. 26-33+38, 2012.
[88] C. Zacharaki et al., "Depletion induced depolarization field in Hf1−xZrxO2 metal-ferroelectric-semiconductor capacitors on germanium,"Appl Phys Lett, vol. 116, no. 18, 2020.
[89] M. Harada, M. Takahashi, S. Sakai, and T. Morie, "A time-domain analog weighted-sum calculation circuit using ferroelectric-gate field-effect transistors for artificial intelligence processors,"Jpn J Appl Phys, vol. 59, no. 4, 2020.
[90] W. Shim and S. Yu, "Technological Design of 3D NAND-Based Compute-in-Memory Architecture for GB-Scale Deep Neural Network,"Ieee Electr Device L, vol. 42, no. 2, pp. 160-163, 2021.
[91] F. Mo et al., "Low-Voltage Operating Ferroelectric FET with Ultrathin IGZO Channel for High-Density Memory Application,"Ieee J Electron Devi, vol. 8, pp. 717-723, 2020.
[92] S. Jindal, S. K. Manhas, S. K. Gautam, S. Balatti, A. Kumar, and M. Pakala, "Investigation of Gate-Length Scaling of Ferroelectric FET,"Ieee T Electron Dev, vol. 68, no. 3, pp. 1364-1368, 2021.
[93] "<Split-Gate FeFET (SG-FeFET) with Dynamic Memory Window Modulation for Non-Volatile Memory and Neuromorphic Applications.pdf>."
[94] J. Min and C. Shin, "MFMIS Negative Capacitance FinFET Design for Improving Drive Current," Electronics- Switz, vol. 9, no. 9, 2020.
[95] M.-Y. Kao, S. Salahuddin, and C. Hu, "Negative capacitance enables GAA scaling VDD to 0.5 V,"Solid State Electron, vol. 181-182, 2021.
[96] S. Yadav, P. Upadhyay, B. Awadhiya, and P. N. Kondekar, "Design and Analysis of Improved Phase-Transition FinFET Utilizing Negative Capacitance,"Ieee T Electron Dev, vol. 68, no. 2, pp. 853-859, 2021.
[97] "<Guidelines for Ferroelectric FET Reliability Optimization_ Charge Matching.pdf>."
[98] K.-W. Chen et al., "Pulse-Mediated Electronic Tuning of the MoS2–Perovskite Ferroelectric Field Effect Transistors,"ACS Applied Electronic Materials, vol. 2, no. 12, pp. 3843-3852, 20201.